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Pipelined RV32IM Processor

May 2025

• SystemVerilog
• RISC-V
• Digital Design

Designed a 5-stage pipelined RV32IM processor in SystemVerilog, implementing:

• Hazard detection
• Data forwarding
• Branch prediction

Verified full functionality across the instruction set using the official RISC-V test suites, cross-checked against waveform-level simulation rather than pass/fail output alone.

Notes

Add a pipeline block diagram, hazard-handling notes, or waveform captures here.