16×4 SRAM Memory Design
November 2025
Designed and simulated a 16×4 SRAM array in 45nm CMOS using Cadence, built from:
- A 6T bitcell
- A 4-to-16 decoder
- Tristate I/O drivers
- Precharge circuitry
The array achieved 90.88 ps worst-case delay across a 2.246 µm² footprint.
Verification
Built a hierarchical testbench validating each subcomponent individually, then full-array read/write behavior across every address — the kind of bottom-up verification that catches a broken bitcell before it hides inside a working-looking array.
Notes
Add layout screenshots, waveform captures, or the testbench structure here.